The problem of having ineffective structures in an integrated circuit design, or the desire to modify a specific design, has been addressed by the use of field-programmable gate arrays, (FPGA). FPGAs been designed to contain the needed row of arrays, as well as additional rows of spare arrays, accessed if needed to replace ineffective counterparts, or to modify a specific design. Recent FPGA designs, feature one-time fusible link structures as possible programmable low resistance interconnect links, if accessed. These additional or spare arrays, or one-time fusible link structures, are sometimes comprised of an antifuse based programmable interconnect structure. The structure consists of an antifuse layer, usually a thin dielectric layer, placed between electrodes or conductive materials. When needed this antifuse material can be ruptured, or converted to a lower resistance layer, via a high voltage electrical pulse, resulting in creation of the replacement array structure.
A thin dielectric layer, comprised of silicon oxide or silicon nitride for example, may be used as the antifuse layer used with the one-time fusible link structure. The dielectric layer has to be thin to allow reasonable programmable voltages to be successfully used. Thus small increases in the thickness of the thin antifuse dielectric layer, due to uniformities in the dielectric layer deposition procedure, may result in inadequate programmed links.
U.S. Pat. No. 5,181,096 to Forouhi describes the use of an amorphous silicon layer, as a part of a composite antifuse layer, sandwiching the amorphous silicon layer with dielectric layers.
U.S. Pat. No. 5,807,786 to Chang (assigned to Taiwan Semiconductor Manufacturing Company, Ltd. as is the present invention) describes a method of using only an amorphous silicon layer as the antifuse layer versus the sandwich structure suggested in Forouhi. To avoid contamination, and additional oxide growth, on the amorphous silicon layer, during patterning procedures, Chang further describes a thin conductive barrier layer is used to overlie, and protect, the amorphous silicon antifuse layer, during specific fabrication sequences. A insulator layer is used to fill in the recesses in the metal (tungsten) plug formed during the metal etch back procedure and is then chemically mechanically polished (CMP) to remove the insulator layer from the top surface of the interlevel dielectric layer (silicon oxide) and from the top surface of the metal plug.
U.S. Pat. No. 5,677,237 to Tsai et al. describes a method of fabricating seamless, tungsten filled, small diameter contact holes. The Tsai et al. process features initially creating a tungsten plug in the small diameter hole and filling or repairing seams or voids in the tungsten plug with an additional layer of selectively deposited tungsten.
U.S. Pat. No. 5,328,865 to Boardman et al. describes a method for making a cusp-free anti-fuse structures.
U.S. Pat. No. 5,804,249 to Sukharev et al. describes a process of forming a tungsten plug by blanket depositing a first bulk layer of tungsten partially filling a via in a dielectric layer. An amorphous or microcrystalline layer of tungsten is then blanket deposited over the first bulk tungsten layer to inhibit the growth of tungsten grains inside the via. A second bulk layer of tungsten is then deposited over the amorphous or microcrystalline layer of tungsten.
U.S. Pat. No. 5,700,726 to Huang et al. describes a process for filling small diameter contact holes with tungsten using two consecutive tungsten depositions. A first tungsten layer is used to coat the sidewalls of the contact hole. A second tungsten layer that will exhibit a significantly slower removal rate than the first layer is then used to completely fill the contact hole.
U.S. Pat. No. 5,656,545 to Yu describes a method of forming planarized tungsten plugs for small diameter contact holes using an RIE (reactive ion etch) etchback process that reduces the seam inherent when filling holes with chemically vapor deposited materials.
U.S. Pat. No. 5,861,671 to Tsai et al. describes a method for fabricating seamless tungsten filled small diameter contact holes. A tungsten plug having a seam or void in deposited in the contact hole then an additional layer of selectively deposited tungsten fills or repairs the seam or void.
U.S. Pat. No. 5,843,839 to Ng describes a method of allowing contact between levels of interconnect metallization structures through the use of a raised tungsten plug structure that permits contact between an underlying active device region and an overlying interconnect metallization structure. The tungsten plug is formed by photolithographic masking and dry etching procedures thus avoiding increasing the size of a tungsten seam in the center of the tungsten plug structure.
U.S. Pat. No. 5,747,379 to Huang et al. describes a process to form seamless tungsten plugs in deep, narrow contact holes. A tungsten plug is formed in a contact hole via tungsten LPCVD processing followed by an RIE etchback and recessing process. A second tungsten LPCVD procedure is then used to fill seams or defects in the first formed tungsten plug followed by another RIE etchback procedure.